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Releases: FPGAwars/iceRegs

v0.2.0

02 Nov 21:01
@Obijuan Obijuan
v0.2.0
de6d650

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v0.2.0 Latest
Latest
  • Remove Verifying errors
  • Testbenches moved to the iceRegs-TB Collection
  • All the registers are generated automatically from templates, using python scripts
Assets 2
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v0.1.0

20 Feb 18:54
@Obijuan Obijuan
v0.1.0
e705ddc

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v0.1.0
  • System registers: from 2 to 32 bits
  • System registers with reset: From 2 to 32 bits
  • Register with load: From 2 to 32 bits
  • Register with load and reset: Fro 2 to 32 bits
  • Examples for the boards:
    • Alhambra-II
    • Nandland go-board
    • Radiona ULX3S-12F
    • Icebreaker
    • Icesugar-1.5
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