		TOPPERS/ASPͥ
		SH12A(GCC)ƥ¸ ߷ץ

		бС: Release 1.7.0
		ǽ: 2011ǯ 719

ΥɥȤϡTOPPERS/ASPͥSH12A(GCC)ƥ¸
߷ץǤ롥
åȰ¸λϡåȰ¸target_user.txt˵ܤƤ
Τǡ⻲ȤΤȡ

----------------------------------------------------------------------
 TOPPERS/ASP Kernel
     Toyohashi Open Platform for Embedded Real-Time Systems/
     Advanced Standard Profile Kernel

 Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
             Graduate School of Information Science, Nagoya Univ., JAPAN
 Copyright (C) 2007-2011 by Industrial Technology Institute,
                                    Miyagi Prefectural Government, JAPAN

 嵭Ԥϡʲ(1)(4)ξ˸¤ꡤܥեȥ
 ܥեȥѤΤޤࡥʲƱˤѡʣ
 ѡۡʰʲѤȸƤ֡ˤ뤳Ȥ̵ǵ롥
 (1) ܥեȥ򥽡ɤηѤˤϡ嵭
     ɽѾ浪Ӳ̵ݾڵ꤬Τޤޤηǥ
     ˴ޤޤƤ뤳ȡ
 (2) ܥեȥ򡤥饤֥ʤɡ¾Υեȥȯ˻
     ѤǤǺۤˤϡۤȼɥȡ
     ԥޥ˥奢ʤɡˤˡ嵭ɽѾ浪Ӳ
     ̵ݾڵǺܤ뤳ȡ
 (3) ܥեȥ򡤵Ȥ߹ʤɡ¾Υեȥȯ˻
     ѤǤʤǺۤˤϡΤ줫ξ
     ȡ
   (a) ۤȼɥȡѼԥޥ˥奢ʤɡˤˡ嵭
       ɽѾ浪Ӳ̵ݾڵǺܤ뤳ȡ
   (b) ۤη֤̤ˡˤäơTOPPERSץȤ
       𤹤뤳ȡ
 (4) ܥեȥѤˤľŪޤϴŪ뤤ʤ»
     ⡤嵭ԤTOPPERSץȤդ뤳ȡ
     ޤܥեȥΥ桼ޤϥɥ桼Τʤ
     ͳ˴Ťᤫ⡤嵭ԤTOPPERSץȤ
     դ뤳ȡ

 ܥեȥϡ̵ݾڤ󶡤ƤΤǤ롥嵭Ԥ
 TOPPERSץȤϡܥեȥ˴ؤơλŪ
 ФŬޤơʤݾڤԤʤޤܥեȥ
 ѤˤľŪޤϴŪʤ»˴ؤƤ⡤
 Ǥʤ

----------------------------------------------------------------------




SH12A¸ϡSH1/SH2/SH2E/SH2A򥿡åȤȤƤ롥SH1/SH2/SH2E/
SH2AˤϤĤΥХꥨ¸ߤХꥨˤäƤϡ
ߴϢΥ쥸䰷㳰ߤοۤʤ롥ΤᡤХꥨ
˰ۤʤʬϥХꥨΥեʬ뤳Ȥˤб
롥
Ūˤϡʲ3ؤʬ䤷Ƥ롣

ƥ¸ʥץå¸
SH1/SH2/SH2E/SH2A̤ơѤʬ
¸
SH1/SH2/SH2E/SH2Aγƥΰ㤤ʬ
åװ¸
SHxxxxηΰ㤤ʬ

ߤϡSH2AξΤߡƤ롣


CPU㳰μ갷

ݡȤCPU㳰ϥɥϥåȥץå˰ۤʤΤǡ
åȥץåե롥

CPU㳰ϥɥֹ

CPU㳰ϥɥֹȤƤϡ٥ֹѤ롥ߤΤNMI
桼֥졼H-UDICPU㳰Ȥư

»

ߤμ갷

ߥϥɥֹȳֹ

ߥϥɥֹ(inhno)ȳֹ(intno)ϡ٥ֹѤ롥

٥ֹɽ

ߤΥ٥ֹTMIN_INTNO(=64)Ϥޤ뤿ᡤΤޤޤͤͥ
ٴΥơ֥ΥǥåѤȡ̵̤ΰ褬ȯ롥
ΤᡤͥǤϡTMIN_INTNO򺹤͡ɽˤѤ
롥

ƥ

/CPU㳰ΥͥȲǡƥȤȽ̤Ƥ롣
ͥȲѿexcnest_countѤƥȤƤ롣
äơƥڤؤˤ
excnest_count
åڤؤ
Բʬ˹Ԥɬפ롣
ͥγߤбϡդɬפǤ롣

(1)ƥȽ sense_context()
excnest_count==0ǤСƥ
ǤʤС󥿥ƥ
(2)CPU㳰ȯΥƥȽ exc_sense_context()
excnest_count==1ǤСƥ
CPU㳰ʬܣƤ롣
ǤʤС󥿥ƥ


ͥ

SH12AǤϡơ쥸SRˤ47ӥåܤ4ӥåȤ˳ͥ
٥ޥʥϡɥγͥ٥ޥIPMˤ֤Ƥ롥IPM
¸Ƥˡͥ٤γɽ-1Ϣ³͡ˤ
ȤǽǤ뤬;פʺӥåȥեȤȿžɬפˤʤ롥
򤱤뤿ˡIPM¸ˤϡSR47ӥåܤФ
ͤȤȤˤ롥ͤͥ٥ޥɽȸƤӡIIPM
񤯤Ȥˤ롥


CPUåե饰

SH12Aϥơ쥸(SR)˳ͥ٥ޥ(IPM)äƤ롥
CPUåե饰εǽʤΤᡤŪCPUå
ե饰¸롥

ޤCPUå֤ѿ(lock_flag)Ѱդ롥

CPUåե饰ꥢƤ֤ϡIPMǥγͥ٥ޥ
ͤꤹ롥δ֤ϡǥγͥ٥ޥϡIPMѤ
롥

ФCPUåե饰åȤƤ֤ϡ
 IPM򡤥ͥΤΤ٤Ƥγ׵ޥ
 (TIPM_LOCK)
 ǥγͥ٥ޥ
ΣĤ⡢⤤ꤹ롥δ֤Υǥγͥ٥ޥϡ
Τѿ(saved_iipm, ɽݻ)Ѱդݻ롥
ƥȤǤϡCPUåְʳǤϡsaved_iipmϾIPMƱ
ͤˤʤ褦ˤ롥

׵饤

SH12Aγߤϡ¢ե⥸塼ߤIRQߤʬǤ줾
찷ۤʤ롥IRQߤϡ°򥵥ݡȤ롥

Ƴߤγͥ٤ϳͥ٥쥸(IPRXX)ˤä
ꤹ롥ΤᡤƳ׵饤ˤɤγͥ٥쥸
ΤɤΥեɤбƤ뤫ξIPR_INFOˤΥơ֥
ipr_info_tbl[]Ѱդ롥
ֹϢ³ƤʤᡤݡȤƤʤֹˤϡaddress
ȥ0ꤷˤֹȽ̤Ǥ롣
ʥݡȤֹϥץꥱˤ餺ץåΥϡ
ͤˤäƷޤΤǡǡȤݻ롣
Υơ֥ΥǥåˤϡֹɽѤ롣

offset8ӥåȤнʬͳ32ӥåȤˤƤ롣
ι¤Τˤȷ֤Ǥǡ
ʤʤ
SHǤ32ӥåȥǡǤʤ̵̤̿᤬롣

typdef struct {
	/* ͥ٥쥸Υɥ쥹 */
	uint32_t address;
	/* եå */
	uint32_t offset;
}IPR_INFO;

IPR_INFO ipr_info_tbl[] = {
	....
}

Υơ֥ζŪƤϡIPR_INFO_TBL_DATAޥȤơåװ
¸롣

¢ե⥸塼ξ硤ե⥸塼˳ͥ٤ǽǤ
롥㤨SCIFϡERI2, RXI2, BRI2, TXI2Ȥ4Ĥγ׵饤
ݡȤ뤬Ƥγ׵饤ФƱͥ٤Ǥ
ʤ
Υ顼åϥƥץ졼ȥեprc.tfǹԤäƤ롣

׵ػߥե饰

SH12AIRCϳ׵ػߥե饰ʤߤ̤˶ػߤ
ϡͥ٥쥸(IPRXX)0ꤹɬפ롥
ͥ٥쥸0ˤ뤳Ȥǳ׵ػߥե饰¸ȡ
δ֡ǥγͥ٤򵭲Ƥΰ褬ɬפȤʤ롥ե
졼ǤΤuint8_tΥơ֥int_iipm_tbl[]Ѱդ롥
ӥåȳƤͥ٤γɽȤɽȤۤʤΤǡ
뤳ȡȿžƤ뤬ӥåȥեȤƤʤ
ͥ٤ꤵƤ뤫ɤϥӥå7ݻ롣
ʥץꥱ˰¸

ơ֥int_iipm_tbl[]˳ǼͤΥӥåȳơ
ӥå03IPRXXꤹӥåȥѥ
ʳͥ٥
ӥå7NOT_CFG_INT_BIT
0:CFG_INTǳͥ٤ꤵƤ롣
1:CFG_INTǳͥ٤ꤵƤʤ

ߡCPU㳰褬ߡCPU㳰ݤȽ
prc_support.S_ret_int_2_ret_exc_2ն򻲾ȡ

SH12AǤCPU㳰/߼ľ˳߶ػߤˤʤäƤʤᡢA
̤γBǽ롣
ʤϥϡɥΥƥ򤱤褦ʤ
ߥϥɥBǥڤؤ򵯤褦ʥӥƤ֤
Bνи̤Υ˥ǥѥåƤޤ2鸵
äƤޤǡAν٤Ƥޤ
ɤᡢ/㳰ޤȤvector_entry
֤Υɥ쥹ϰʤǥѥå˥꥿󤹤롥


Ԥsleep̿ˤĤ
prc_support.S_dispatcher_2ն򻲾ȡ

ǥѥåνиǼ¹Ԥ٤ʤ(schedtsk==NULL˾ϡ
sleep̿ˤäƥץåϥ⡼ɤڤؤƳԤ򤷤
롣

ߵĸsleep̿¹ԤƤ뤿ᡢߵ̿μ¹˳
׵᤬äƤʤ뤤ϳߵľ塢sleep̿¹˳
׵᤬äˡߵ̿μ¹Ԥȶ˳ߤդ졢
sleepޤޤˤʤꡢreqflgΥå˿ʤޤʤ
1msec˥޳ߤ뤿ᡢºݤˤsleepޤޤȤȤ
ʤ
ϡߤεĤsleep֤ؤΰܹԤȥߥå˼¹ԤǤʤ
Ȥ˵롣
褹뤿ᡤrte̿ΡPC,SRٱ䥹åȤ̿򡢳
ߤȤԲʬ˼¹ԤפȤͤѤߤεĤȾϥ⡼
ɤؤΰܹԤԲʬ˹Ԥ

IRQ׵ΥꥢSH2Aͭ

IRQRR쥸١ߡ꡼ɤơ ӥåȤ0񤭹ࡣ
ǤϡʲΤ褦ʼȤƤ롣

Inline void
i_begin_int(INTNO intno)
{
    SIL_PRE_LOC;
    uint32_t irqpr, bitptn;
    if (INTNO_IS_IRQ(intno)) {
        /*
         * ١ߡ꡼ɤơ ӥåȤ0񤭹ࡣ
         *  ѿbitptnѤƤΤϡߥåζ֤
         *  û뤿
         */
        bitptn = ~(0x01U << INTNO_TO_IRQNO(intno));
        SIL_LOC_INT();
        irqpr = sil_reh_mem((uint16_t *)IRQRR_h);
        irqpr &= bitptn;
        sil_wrh_mem((uint16_t *)IRQRR_h, irqpr);
        SIL_UNL_INT();
    }
}

IRQRR쥸֡ߥå֤ˤƤΤϡʲΤ
ʥɤǤ롣

3γߤͤ롣
ͥ٤ϡl > m > nνȤ롣
ʳlͥ٤⤤

1.  mγߤȯ(mӥåȤå)
2.  mγߥϥɥ餬¹(nϳ߶ػ)
3.  IRQRR꡼(l = 0, m = 1, n = 0)
4.  lγߤȯ(lӥåȤå)
5.  lγߥϥɥ餬¹(nϳ߶ػ)
6.  nγߤȯα(nӥåȤå)
7.  IRQRR꡼(l = 1, m = 1, n = 1)
8.  IRQRR饤(l = 0, m = 1, n = 1)
9.  lγߥϥɥ齪λ
10. mγߥϥɥƳ
11. IRQQ饤(l = 0, m = 0, n = 0)

11ʳ n ꥢǽ롥

ߵĶ֤ûջSH2Aͭ

SHޥϳ׵᤬ä硢
CPU
ߥȥINTC
ξǵĤˤΤߡߤդ롣
ldc̿ˤѹ줿SR쥸IӥåȤξ
CPUINTCãޤǤٱ䤬ꡢ
ΤߤߤĤƤӤ롣
ʤδ֤ϡߤդʤ
ߤػߤȵĤǤٱαƶۤʤ롣

ߤػߤldc̿
CPUǳߤػߤǤΤǡٱϹθʤƤ褤
ߤĤldc̿
CPUINTCξߤĤʤȳߤϼ
դʤΤǡٱαƶ롣

SH2Aξ硢ldc̿μ¹Ը塢3Icycʬ
ǳߥȥƤͭˤʤ롣
ʥѥʤΤǡnop̿ǣĤ

սꡧ
prc_support.S_dispatcher_2ն
sleep̿Ȥʤ
ʲ̿Ȥ߹碌Ϣ³Ƽ¹ԤƤս
	x_unlock_cpu()/x_lock_cpu()/x_set_ipm()
	SIL_UNL_INT()/SIL_LOC_INT()
	
嵭νϢ³Ƽ¹Ԥ硢x_unlock_cpu()ǳߵĤ
ͭˤʤx_lock_cpu()ǳ߶ػߤƤޤȳߤ
դʤ
ɤᡢåȰ¸ǰʲΥޥȾ嵭
3սnop̿롣x_set_ipm()ľ
x_lock_cpu()/x_set_ipm()¹Ԥ뤳ȤϹͤˤΤǡ
x_set_ipm()ˤĤƤٱθƤʤ

LDC_NOP_DISPATCHER
_dispatcher_2nop̿
LDC_NOP_SET_SR
set_sr()nop̿
LDC_NOP_SIL_SET_IIPM
SIL_UNL_INT()nop̿

ʤLDC_NOP_SET_SRLDC_NOP_SIL_SET_IIPMϥ饤󥢥֥
ǻѤ뤿ᡢɬפʿnop̿" "ǰϤळȡ

㡧
#define LDC_NOP_SET_SR			"nop; nop"


sh1/sh2/sh2eǤϤΤ褦ٱϤʤ
ޤsh2aǤ̿ᥭå夬̵ʾ̿եå
3IcycʬʾΥ뤬Τǡ嵭Τ褦Ϥʤ
¢RAM֤̿

åapsh2a_gccˤͻ
ե֥̤顢ɬפnop̿οƤ롣
sh-elf-gcc 4.3.2Ŭץ-O2

i_unlock_cpu();
i_lock_cpu();
Ϣ³Ƽ¹ԤƤ
kernel/wait.cwait_tmout()

i_unlock_cpu
    82e6:	01 02       	stc	sr,r1
    82e8:	d3 1c       	mov.l	835c <__kernel_wait_tmout+0xac>,r3	! c004e1c <__kernel_saved_iipm>
    82ea:	02 f0 ff 0f 	movi20	#-241,r2
    82ee:	21 29       	and	r2,r1
    82f0:	62 32       	mov.l	@r3,r2
    82f2:	21 2b       	or	r2,r1
    82f4:	41 0e       	ldc	r1,srߵ

i_lock_cpu
    82f6:	02 02       	stc	sr,r2
    82f8:	01 00 00 f0 	movi20	#240,r1
    82fc:	22 19       	and	r1,r2
    82fe:	32 10       	cmp/eq	r1,r2
    8300:	89 02       	bt	8308 <__kernel_wait_tmout+0x58>
    8302:	00 02       	stc	sr,r0
    8304:	20 1b       	or	r1,r0
    8306:	40 0e       	ldc	r0,sr߶ػߡ̿ᡡnop̿ɬפʤ


SIL_UNL_INT();
SIL_LOC_INT();
Ϣ³Ƽ¹ԤƤ

SIL_UNL_INT();
     4e6:	02 f0 ff 0f 	movi20	#-241,r2
     4ea:	64 93       	mov	r9,r4

     4ec:	01 02       	stc	sr,r1
     4ee:	21 29       	and	r2,r1
     4f0:	21 8b       	or	r8,r1
     4f2:	41 0e       	ldc	r1,srߵ
     4f4:	00 09       	nop	LDC_NOP_SIL_SET_IIPMˤ
     4f6:	00 09       	nop	줿nop̿

SIL_LOC_INT();
     4f8:	00 02       	stc	sr,r0
     4fa:	08 00 00 f0 	movi20	#240,r8
     4fe:	28 09       	and	r0,r8
     500:	cb f0       	or	#-16,r0
     502:	40 0e       	ldc	r0,sr߶ػߡܣ̿᣶̿


»
FPUΰ
ܥͥǤSH2A-FPUFPUϥݡȤƤʤ

ȥ쥸ΰ
ܥͥǤϥХ١쥸GBRץơ֥
١쥸TBRϥݡȤƤʤ

IRQüҤν
CFG_INTǻꤵ줿IRQüҤν򥫡ͥ¦Ǥ
SH2-AǤϡIRQֹ椫³üҤդ˷ޤʤ
ʣüҤǤˤᡢIRQüҤνϥݡ
Ƥʤüֹ˰¸ʤߥȥν
ԤäƤ롣

=====================================================================
               åȰ¸ȯԸξ
=====================================================================

SH12A¸ϡʲΤ褦3ؤʬ䤵Ƥ롣

ƥ¸ʥץå¸
SH1/SH2/SH2E/SH2A̤ơѤʬ
ե̾ˤƬprc_դ롣
Makefileξϡդ롣
¸
SH1/SH2/SH2E/SH2Aγƥΰ㤤ʬ
ե̾ˤƬshx_դ롣x1,2,2e,2aΤ줫
Makefileξϡդ롣
åװ¸
SHxxxxηΰ㤤ʬ
ե̾ˤƬshxxxx_դ롣
xxxxϷ֤ɽ


ݡȥץåɲ

ݡȤåפɲäˤϡʲΥեɬפ
롥¾Υե뤬ɬפʾϡåפη֤Ƭդե
åȰ¸饤󥯥롼ɤФ褤

¸
̾ΤshxȤ롣
Makefile.shx		MakefileΥ¸
shx.tf			kernel.tfΥ¸
shx_config.h		ͥΥ¸

åװ¸
ݡȤåפη֤shxxxxȤ롣
shxxxx.tf			kernel.tfΥåװ¸
shxxxx_config.h	ͥΥåװ¸
shxxxx.h			ϡɥ񸻤Υإåե


¸åװ¸ˤϡʲΥޥؿ롥
åȰ¸ǤϡѤåפΥåװ¸Υե򥤥
롼ɤ롣
åװ¸Υե뤫ϡ¸ƥ¸ν˥
󥯥롼ɤ롣
åװ¸˳ե뤬ʤϡ¸Υե򥤥
롼ɤ롣¸˳ե뤬ʤϥƥ
¸Υե򥤥󥯥롼ɤ롣



Makefile.shx		MakefileΥ¸

ѥ륪ץ COPTS
㡧COPTS := $(COPTS) -m2a-nofpu

ޥ CDEFS

ͥ륪֥ȥե̾ KERNEL_COBJS
ޤμʤɤ롣

¸ط
kernel_cfg.timestampϥѥtfեshx.tf,shxxxx.tf˰¸
Τǡΰ¸ط򵭽Ҥ롣

¾
åȰ¸Makefile.targetǰʲΤ褦ѿƤ
ΤǡѤƤɤ
Makefile.targetMakefile.shxMakefile.prcνɤ߹ޤ롣

	#
	#  ܡ̾å̾ƥ̾ȯĶ̾
	#
	CHIP  = sh7211

	#
	#  ƥ¸ؤΥѥ
	#
	PRCDIR = $(SRCDIR)/arch/$(PRC)_$(TOOL)


shx.tf			kernel.tfΥ¸

NMIγֹ	TINTNO_NMI
°ΥåȰ¸Ѥӥå	TARGET_INTATR
CFG_INTǤ°Υꥹ
IRQߤǻѤǤ°	valid_irq_intatr_list
NMIǻѤǤ°			valid_nmi_intatr_list

shx_config.h		ͥΥ¸

μ
̿᥻åȡˤμ

Ѥץåμ򥿡åȰ¸ Makefile.target
PRC_COREȤ롥ߤϡPRC_COREsh2aξΤߡƤ롣
sh1/sh2/sh2e/sh2aΤ줫뤳ȤꤷƤ롣
ޤѤǤ̿᥻åȤμʲΥޥȤơ¸Υ
롼ɥե㡧sh2a_config.hˤ롣
SH1̿ˤĤƤϡ٤ƤΥǥݡȤΤǡäʤ

#define TOPPERS_SUPPORT_SH2_INSTRUCTION
#define TOPPERS_SUPPORT_SH2E_INSTRUCTION
#define TOPPERS_SUPPORT_SH2A_INSTRUCTION

INTNO_IS_IRQ(intno)	IRQߤɤȽꤹ뤿Υޥ
INTNO_TO_IRQNO(intno)	ֹ椫IRQֹؤѴޥ
void irc_initialize(void)
						ߥȥν
void x_config_intatr(INTNO intno, ATR intatr)
						ߤ°
void i_begin_int(INTNO intno)
						ߥϥɥɬפIRC

TINTNO_NMI			NMIγֹ

å

shxxxx.tf			kernel.tfΥåװ¸

CFGѤΥƥץ졼ȥեˤϰʲѿ롥åȰ¸
CFGѥƥץ졼ȥեǤϡprc.tf 򥤥󥯥롼ɤˡ
륿åȥץåCFGѥƥץ졼ȥե򥤥󥯥롼ɤ
ȡ
ޤshxxxx.tfkernel_cfg.timestampΰ¸طMakefile.target
롣

ͭʳֹ桤ߥϥɥֹ桤CPU㳰ϥɥֹ

$INTNO_VALIDʥͥγߤֹޤࡣ
$INHNO_VALIDƱ
$EXCNO_VALID

Ʊͥ٤ꤷʤФʤʤֹΥꥹ

$same_intpri_list
-1򥻥ѥ졼Ȥ롣

shxxxx_config.h	ͥΥåװ¸

CPU㳰ֹ˴ؤ

  TMIN_EXCNO : CPU㳰ֹκǾ
  TMAX_EXCNO : CPU㳰ֹκ
  TNUM_EXC   : CPU㳰ֹ(ѡʾϤδ֤⥫Ȥ)

ߥϥɥֹ˴ؤ

  TMIN_INHNO : ߥϥɥֹκǾ
  TMAX_INHNO : ߥϥɥֹκ
  TNUM_INH   : ߥϥɥ(ѡʾϤδ֤⥫Ȥ)

ֹ˴ؤ

  TMIN_INTNO : ֹκǾ
  TMAX_INTNO : ֹκ
  TNUM_INT   : ߿(ѡʾϤδ֤⥫Ȥ)
  
  TMIN_INTNO_IRQ : IRQߤγֹκǾ
  TMAX_INTNO_IRQ : IRQߤγֹκ

׵饤ͥ٥쥸

  IPR_INFO_TBL_DATA

ͥ٥쥸νؿ

  Inline void init_ipr(void);

shxxxx.h			ϡɥ񸻤Υإåե

㳰٥ֹ
yyyyyyyy_VECTORyyyyyyyyCPU㳰װ
ߥ٥ֹ
yyyyyyyy_VECTORyyyyyyyyϳװ
äNMIγߥ٥ֹNMI_VECTORȵꤹ롣
¢ڥեΥ쥸
ߥȥ

ꥢ륤󥿡ե
ԥե󥯥󥳥ȥ
å̿λ
ٱ䥹åȤldc֤̿ȥå̿ˤʤ
sh7619(sh2Ethernet)Υˤ
TOPPERS_LDC_IS_SLOT_ILLEGAL_INSTRUCTIONޥ
prc_support.SγĽ꤬異֥ldc̿ٱ䥹å
֤ʤ褦ڤؤ롣

ޥɥ饤
¢ޤȤơڥޥåCMTꤷ
prc_cmt.h/c/cfgΤѰդƤ롣
ۤʤ¢ޤѤϡե
åȰ¸饤󥯥롼ɤ롣

ꥢɥ饤
¢ꥢǥХȤơFIFO¢ꥢ륳ߥ˥
󥿡եSCIFꤷpdic/shsh_scif.h/cΤѰդƤ롣
PDICȤƥǥ쥯ȥʬƤΤϡSH1SH4γƥ꡼
ͭ뤿
ۤʤΥꥢǥХѤϡե
åȰ¸饤󥯥롼ɤ롣

åȰ¸

ߤĤldc̿ٱˤĤ

ʲΥޥ롣
ܺ٤ϡΥɥȤΡ֡ߵĶ֤ûջ
򻲾

LDC_NOP_DISPATCHER
_dispatcher_2nop̿
ꡧtarget_config.h
LDC_NOP_SET_SR
set_sr()nop̿
ꡧtarget_config.h
LDC_NOP_SIL_SET_IIPM
SIL_UNL_INT()nop̿
ꡧtarget_sil.h


ѹ

'11/07/19 
NMIγֹˤĤɵ

'11/01/07 
kernel_cfg.timestampshxxxx.tfΰ¸ط
Makefile.targetMakefile.shx˰ư
ȼåȰ¸Makefile.targetѿCHIPɲ

'10/12/16 
kernel_cfg.timestampshx.tfshxxxx.tfΰ¸طˤĤɵ

'10/09/22 Release 1.6.0
Сֹ򹹿

'10/07/05 
¾Υ˰ܿݤΥޥɥ饤Фȥꥢɥ饤Фν
ɵ

'10/07/02 
֥åȰ¸ܡפɵ
ʲΥޥ
LDC_NOP_DISPATCHER
LDC_NOP_SET_SR
LDC_NOP_SIL_SET_IIPM
ֳߵĶ֤ûջפ

'10/06/08 
ֳߵĶ֤ûջפɵ

'09/05/13 Release 1.4.0
Сֹ򹹿

'09/04/10 
TOPPERS_LDC_IS_SLOT_ILLEGAL_INSTRUCTIONޥɲ

'09/04/02 
shxxxx.tfƤʲѿ
EXCNO_RANGEINTNO_RANGEINHNO_RANGE
TMIN_INTNO_IRQTMAX_INTNO_IRQ
set_irc_ipr()
shx_config.hprc_config.hذư
i_begin_int()
prc_config.hshx_config.hذư
init_irc(), set_irc_ipr()
줾irc_initialize(),irc_set_ipr()˥͡

'09/03/31 
ʲ2ɲ
ߡCPU㳰νиǤΥƥȽ̤ˤĤ
¹Ԥ٤ʤξϥ⡼ɤˤĤ

'09/03/27 
桼ޥ˥奢뤫ʬΥ

