Control Dependency

Control dependency created in a pipeline when a branch or Transfer of Control (TOC) instruction can alter the program flow. This makes the next sequential instruction potentially unwanted until the branch outcome is resolved.

1. Instruction Classification After Decoding

2. Branch Penalty

Branch Penalty = k – 1, where k = stage at which target address becomes available.

• Example: If the target address is known at the end of stage 2, tpenalty = 2 – 1 = 1 cycle.
• In RISC pipelines, the target address is typically available at the end of the 2nd stage (ID) → Penalty = 1 cycle.

Branch Target Address Availability

Note: Full resolution (target + condition) often completes in Execute stage.

Flushing Unwanted Instructions

• Overlapped execution continues until branch outcome is known.
• If branch is taken, sequentially fetched instructions are unwanted.
• These instructions are flushed (discarded).
• The process of removing unwanted instructions is called Flush or Stall.

# of stalls due to branch = Branch Penalty

Ideal vs Actual CPI

Average Instruction Completion Time (CT)

Method 1

Avg Instr CT = 1+(# of instructions that create stalls)+(# stalls due to branch)

Method 2

Avg Instr CT=1+(Branch instruction frequency×# stalls per branch)

Sources of Control Dependency

Control Dependency is Created in Pipeline:

• Branch Instruction
• Program Control
• Function Call
• Transfer of Control Instruction(unconditional TOC | conditional TOC)

Example: 5-Stage Pipeline (IF → ID → EX → MEM → WB)

Instruction Sequence

• Assume 5-stage pipeline & I2 is the Branch instruction.
• Assume the target address of the Branch Instr is available at the end of last stage.

• S = Stall
• I₃,I₄, I₅, I₆ → Unloaded (fetched but flushed) BI₁,
• BI₂ → Correct path instructions (waited during stalls)