In Computer Organisation and Architecture (COA), pipelining is a technique used to increase the instruction throughput of a processor. It allows multiple instructions to be executed simultaneously by dividing the execution process into several stages, where each stage performs a part of the instruction.
However, when multiple instructions overlap, conflicts or hazards can occur. To manage this effectively, pipeline scheduling is used — it decides when and how each instruction enters the pipeline to ensure smooth and efficient execution.
Key Points:
- Pipeline scheduling determines the order and timing of instruction execution in a pipeline.
- The goal is to minimise stalls and delays caused by instruction dependencies or resource conflicts.
- It helps achieve maximum pipeline utilisation and reduces idle stages.
- Scheduling ensures that data hazards (like read after write) are avoided or resolved properly.
- Techniques like forwarding, stalling, and reordering are used for effective pipeline scheduling.
Types of Pipeline Scheduling
Static Scheduling
- Done at compile time by the compiler.
- The compiler rearranges instructions to avoid pipeline conflicts.
- No hardware intervention during execution.
- Example: Loop unrolling in compilers.
Dynamic Scheduling
- Done at runtime by hardware using mechanisms like Tomasulo’s algorithm.
- Allows out-of-order execution to avoid stalls.
- Helps when instruction dependencies are unknown at compile time.
Example:
Let’s say we have three instructions:
I1: R1 = R2 + R3
I2: R4 = R1 + R5 I3: R6 = R7 + R8
Now, I1 executes while I2 waits — no idle pipeline stage occurs, and performance improves.
Challenges in Pipeline Scheduling
- Data Hazards: When one instruction depends on the result of another.
- Structural Hazards: When hardware resources are shared or limited.
- Control Hazards: Caused by branch or jump instructions.
- Complex Hardware: Dynamic scheduling adds design complexity
