When a jump happens in the program, the computer might fetch the wrong instruction by mistake. This wrong instruction runs and can mess up the program. This problem is called control dependency. To fix it, we stop fetching new instructions for a moment.
- We do this by putting a "NOP" (do-nothing) instruction right after the jump.
- This stopping action is called freezing the pipeline.
Pipeline Freeze + NOP (Flush & Stall)
Technique: Insert NOP after branch → Freeze the pipeline
| Address | Instruction |
|---|---|
| 1000 | I₁ |
| 1001 | I₂ |
| 1002 | I₃ (JMP .2000) |
| 1003 | NOP |
| 1004 | I₄ |
| ... | ... |
| 2000 | B.I₁ |
| 2001 | B.I₂ |
Note: The NOP is inserted after the jump to freeze the pipeline and prevent unwanted instructions from being fetched.
| Instruction | C1 | C2 | C3 | C4 | C5 | C6 |
|---|---|---|---|---|---|---|
| I₁ | IF (PC: 1001) | ID | EX | MA | WB | |
| I₂ | IF (PC: 1002) | ID | EX | MA | WB | |
| I₃ | IF (PC: 1003) | Unconditional TOC ID (PC: 2000, PC: 2004) | EX | MA | ||
| I₄ | IF (PC: 2000, PC: 2004) | ID | EX | |||
| B1₁ | IF (PC: 2001) | ID | ||||
| B1₂ | IF (PC: 2002) |
Key Points:
- I₃ = Unconditional branch (jump) instruction
- NOP inserted = Delayed branch slot filled with No Operation
- Actual sequence: I₁ → I₂ → I₃ → NOP → B1₁ → B1₂
- PC values: Shows branch target address (2000) and next sequential address (2004)
- Stage abbreviations: IF = Fetch, ID = Decode, EX = Execute, MA = Memory Access, WB = Write Back
This demonstrates delayed branching in action - the NOP instruction executes while the branch is resolved.
Branch Prediction
Predict the outcome of a branch before it is resolved to avoid stalling. Branch Prediction is divided into two types:
- Static → Fixed guess (same every time)
- Dynamic → Changes based on past behavior
Static Branch Prediction
- Branch is always Taken: In this we Assume Every time Branch is Taken. So the next instruction address is Target Address of the branch instruction.
- Branch is Never Taken: In this we Assume Branch is never taken, so the next instruction address is the next sequential instruction address.
Dynamic Predictors:
- 1-bit Predictor: Remembers last outcome
- 2-bit Saturating Counter: More robust (hysteresis)
- Correlating Predictor: Uses global/local history
- GShare / Perceptron / TAGE: Advanced tournament predictors (used in modern CPUs)
Benefit: Reduces misprediction penalty (e.g., Intel/AMD use TAGE-like predictors)
Note: If Prediction goes Wrong (Wrong Prediction) then have to Suffer Stalls.
Delayed Branch
It is a compiler technique, so the compiler rearranges the code, if possible, to arrange or substitute the NOP instruction after the branch instruction. If not possible to rearrange, it preserves the execution path.
Note: To minimize the control dependency stalls, a software technique is used i.e., Delayed Branch.
