Managing 3D-IC Design And IP


By Keith Felton and Todd Burkholder The trend towards multi-chiplet heterogeneous integration is here to stay. It promises faster innovation, more powerful and specialized devices, and greater design flexibility. However, realizing its potential hinges on our ability to manage the complexity that comes with it. However, with this newfound modularity comes a significant challenge: managing... » read more

Designing Multi-kW Power Delivery In 3D Heterogeneously Integrated Systems (U. of Minnesota)


Researchers at the University of Minnesota published a technical paper titled “Toward Multi-kW Power Delivery Methodologies for Advanced 3D Heterogeneous Integration.” Abstract Excerpt: “Computationally powerful systems require significant power for computation: reliable and robust power delivery is a major challenge in light of high power densities and pin count bottlenecks. Thi... » read more

Chiplet Co-Design Framework Reduces Energy and Design Costs for AI Accelerators (University of Michigan)


Researchers at the University of Michigan published a technical paper titled “Fengshui: Demystifying Chiplet Ecosystem and Bespoke Neural Network Accelerator Codesign.” Abstract Excerpt: “This paper introduces Fengshui, a chiplet ecosystem and accelerator co-design framework that jointly optimizes chiplet pool composition and bespoke application-specific integrated circuit ... » read more

Open Benchmark Evaluates AI Thermal Models for 2.5D and 3D ICs (UTS, TU Munich, ShanghaiTech)


Researchers at the University of Technology Sydney, ShanghaiTech University, and Technical University of Munich published a technical paper titled “IC-ThermBench: An Open, Progressive Benchmark for Generalizable 2.5D/3D-IC Thermal Learning.” Abstract Excerpt: “We introduce IC-ThermBench, an open and progressive benchmark that combines established 3D-IC steady-state, transie... » read more

Unified Chiplet Network Scales Neuromorphic Computing Systems (Heidelberg University)


Researchers at Heidelberg University published a technical paper titled “A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System.” Abstract Excerpt: “To overcome the challenges of scaling analog designs, chiplet-based designs offer a promising approach with cost and flexibility advantages over monolithic scaling. Implementing a chi... » read more

Why Package Digital Twins Are So Hard To Build


Key Takeaways: Package twins must track what manufacturing actually builds, not just design intent. Missing process and supplier data can undermine otherwise precise simulations. Coupled physics and ongoing calibration keep models tied to physical reality. A chiplet can be fully characterized, tested, and considered known good, but none of that guarantees it will stay that w... » read more

From Silicon To Systems: Heterogeneous Integration As The Engine Of AI Performance


We are in the middle of one of the most important shifts our industry has seen in decades. The internet economy transformed how people connect, communicate, and consume information. The AI economy is redefining a more fundamental layer: how compute is architected, delivered, scaled, and optimized. AI workloads are creating demands for power, memory bandwidth, I/O, thermal performance, and syste... » read more

Why SoC Interconnects Have Outgrown the Bus


This technical white paper explores why modern AI, automotive, and chiplet-based SoCs are outgrowing traditional interconnects and how advanced NoC architectures and coherent subsystem IP can address the industry's next-generation scalability, safety, and performance challenges. The shared-bus and crossbar interconnects that served the SoC industry for two decades are running out of room. AI... » read more

AMBA Over UCIe: Building Coherent Multi-Die Systems


As computing systems evolve to meet the demands of AI, data centers, and high-performance workloads, the challenge is no longer just about building powerful IP blocks. It is about connecting them efficiently at scale. The transition from monolithic SoCs to chiplet-based architecture has unlocked new possibilities in modularity and scalability. However, it has also introduced a critical r... » read more

Advanced Packaging Changes The Rules For Semiconductor Health And Performance Management


Systems-in-Package (SiPs) are enabling the next generation of Agentic and Physical AI across cloud, telecommunications, mobile, automotive and high-performance computing platforms. As infrastructure evolves from monolithic devices toward heterogeneous architectures, advanced packaging is becoming increasingly critical to achieving the required performance, bandwidth and power efficiency. But as... » read more

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