Chip Industry Week In Review

By The SE Staff - 25 Sep, 2026 - Comments: 0

AI moves deeper into chip design Cadence released a new agent for spec-to-RTL generation and early PPA optimization as part of its ChipStack AI Super Agent, reporting about 24% lower area and 18% lower power versus pure foundation model code generation. The release is part of a broader move toward specialized AI agents across chip-design workflows, which is creating new challenges aroun... » read more

Chip Industry Week in Review

By The SE Staff - 11 Sep, 2026 - Comments: 0

SPIE News from this week’s SPIE Photomask Technology + Extreme Ultraviolet Lithography conference: ASML and TSMC are launching an industry initiative to transition high-NA EUV lithography from current 6-inch photomasks to larger 12-inch masks, which could improve scanner productivity and eliminate some stitching constraints. The companies are targeting a 12-inch mask pilot line by 203... » read more

Silent Data Errors Redefine Test Coverage And Fleet Maintenance Strategies

By Laura Peters - 10 Sep, 2026 - Comments: 0

Key Takeaways: A chip can pass ATPG, transition-fault, stuck-at, and at-speed structural testing and still produce an incorrect arithmetic result that propagates until a wrong output surfaces. Targeted functional tests at the system level and in the field can catch more of these stealth defects. Broad and deep functional test content and stress tests can identify SDEs in commercial proc... » read more

Can GPUs Continue To Dominate AI Compute?

By Geoff Tate - 09 Sep, 2026 - Comments: 0

GPUs are 70% of installed worldwide AI compute capacity by manufacturer (see figure 1), with custom silicon accounting for 30%, primarily Google and Amazon. Fig. 1: Current installed worldwide AI compute capacity by manufacturer. Source: Epoch.ai Installed AI compute capacity has grown 17X in three years. In 2023, Nvidia had 90% share and Google 10%. Custom AI compute took 20% share i... » read more

Chip Industry Week In Review

By The SE Staff - 04 Sep, 2026 - Comments: 0

Innovations Hong Kong Polytechnic University-led researchers developed a 2D tunnel transistor that can switch at lower voltages than conventional MOSFETs while maintaining strong current performance. The device was demonstrated at room temperature on centimeter-scale silicon substrates and meets IRDS requirements for next-gen integrated circuits, pointing toward lower-power future chips. Ts... » read more

Chip Industry Week In Review

By The SE Staff - 21 Aug, 2026 - Comments: 0

Sticker shock Gartner says AI inferencing costs per agentic workflow will increase fivefold through 2028, with the rate of innovation outpacing the cost curve. Samsung increased pricing on new 4nm, 5nm, and 8nm foundry orders by up to 15%, reports Reuters. Its Pyeongtaek 4nm line is reportedly running at full capacity. SMIC also raised prices per last week's earnings call. New offeri... » read more

Chip Industry Technical Paper Roundup: Aug. 18

By Linda Christensen - 18 Aug, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.5D PIM Chiplet Architectures Washington State University, University of Wisconsin–Madison SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced N... » read more

Chip Industry Week In Review

By The SE Staff - 14 Aug, 2026 - Comments: 0

Data centers UC Berkeley experts argue that AI progress does not require ever-larger data centers. Smaller open-source models are becoming capable enough for many tasks while using far less compute, energy, and water — and increasingly they could run on local HW. A 19-company coalition within the Open Compute Project unfurled a plan for a standardized silicon photonics-ready infrastr... » read more

Copper’s Grip On AI Scaling Is Starting To Slip

By Bryon Moyer - 13 Aug, 2026 - Comments: 0

Key Takeaways: Scale-up may go beyond one rack and may use optical interconnects for longer runs. Optical circuit switching may expand beyond Google. Scale-in is a new scaling term referring to the scale of a single server board. Data-center network fabrics are undergoing another architectural shift as optical interconnects assume a larger role in AI-cluster connec... » read more

Failure Analysis HW Enables System-Level Debug For 3D ICs (Google, TU Delft)

By Technical Paper Link - 10 Aug, 2026 - Comments: 0

Researchers from Google and Delft University of Technology published a technical paper titled “Innovative FA Hardware Solution to Enable System-Level Debug of 3D ICs.” Abstract Excerpt: "This paper presents a novel Failure Analysis (FA) hardware and sample preparation solution that enables System-Level FA on mobile System-on-a-Chip (SoC) PoP devices, where the DRAM is stacked atop the lo... » read more

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Chip Industry Week In Review

Chip Industry Week in Review

Silent Data Errors Redefine Test Coverage And Fleet Maintenance Strategies

Can GPUs Continue To Dominate AI Compute?

Chip Industry Week In Review

Chip Industry Week In Review

Chip Industry Technical Paper Roundup: Aug. 18

Chip Industry Week In Review

Copper’s Grip On AI Scaling Is Starting To Slip

Failure Analysis HW Enables System-Level Debug For 3D ICs (Google, TU Delft)

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